Santa Clara, CA (PRWEB)
November 08, 2017
Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced immediate availability of the Visual Verification Suite 2017.3.
The Visual Verification Suite provides an advanced integrated RTL debugging, constraint generation and clock domain crossing analysis and debug environment, so that designers can verify as they code. With the suite, RTL developers produce the highest level of quality code, in the least amount of time. It is proven to help avoid costly and time-consuming design re-spins due to simulation vs. hardware mismatches, structural issues, invalid constraints and metastability issues. The new release provides updates to the suites Analyze RTL’s advanced static and formal analysis, Clock Domain Crossing (CDC) analysis and the Management Dashboard tools.
The release features up to 12X faster runtimes for CDC Analysis, enabling faster iterations of analysis and debug. “With the enhanced CDC infrastructure, built in FPGA libraries and recently patented User Grey Cell technology which enables CDC analysis through encrypted IP, we are setting the bar in ease of use and performance,” said Scott Aron Bloom, CTO at Blue Pearl.
The release also features enhancements to the Xilinx® Vivado® Design Suite integration introduced in 2017.2. Users can now use the Blue Pearl Tcl App, to track key metrics run-to-run from Vivado, such as Max Frequency, Power, Device Utilization and display it in the Management Dashboard’s graphs and new table views along with results from the Visual Versification Suite. The Management Dashboard streamlines design reviews, audits, signoff and revision control.
Engineered to maximize RTL bug find/fix rates for both novice and expert users, the Visual Verification Suite 2017.3 uniquely provides easy…